1. Field of the Invention
This invention relates to computer circuitry and, more particularly, to handshake circuitry at a computer bus interface for connecting asynchronous clocked modules.
2. History of the Prior Art
The typical interface system for transferring information between two computer systems or modules is a synchronous interface system, one in which the two systems are operated by the same clock. Joining the two system is usually a data bus for carrying information, an address bus for carrying addresses, and control lines for accomplishing a so-called "handshake" between the two systems. Normally a write line, a read line, and an acknowledge line are required for transferring signals between the two systems to accomplish the handshake operation.
In the normal synchronous interface where both computer systems are running on the same clock, the computer system wishing to read information from a second system provides a read signal on the read control line during a first clock period. In response to that signal, the second system samples the read line connecting the two systems during a second clock period, finds the data at the address designated and places the data on the data bus during a period defined by the address of the particular data, and finally returns an acknowledge pulse on the acknowledge line to indicate that the data is at the data bus ready to be transferred. Before additional information may be read through the interface system, an additional clock period is necessary to terminate the original read signal, and another clock period to terminate the acknowledge signal.
Since each of the signals on the handshake lines is driven by the system clock, the read handshake operation in a synchronous system where the same clock controls both systems may require as many as four clock cycles. This does not include the time required to obtain the data from the addressed position which varies depending on the address of the data and on the addressed device.
Where the two systems joined by the bus operate at different clock frequencies, it is necessary that the incoming and outgoing handshake signals be synchronized to each of the two systems as they travel in each direction. Consequently, an incoming read signal must be synchronized to the clock of the receiving system while the outgoing acknowledge system must be synchronized to the clock of the sending system. The normal manner in which this is accomplished by the prior art is to use two stages of flip-flops on each handshake line, each stage being driven by the clock of the system receiving the particular signal. The use of two stages of flip-flops to receive the handshake signals adds at least two additional clock periods to each step of the synchronization in an asynchronous interface of the prior art.
There have been asynchronous interface systems designed which utilize various techniques to speed up aspects of the handshake operation. For example, in a write operation where the data is immediately available, multiple pipeline stages may be used to move the synchronization problem from the interface circuitry into one of the two systems, a technique which moves the bottleneck from the interface system but does not remove the bottleneck.
However, in the read handshake operation, the data must be found at some address of the second system before it may be transferred to the requesting system. Consequently, a read handshake operation cannot utilize the same sort of pipeline circuitry used in the write handshake to remove the delay caused by synchronization between two asynchronous systems from the interface. This is true for two reasons. First, as explained, the read data is not immediately available (as is the write information) so the data cannot be immediately transferred. Second, obtaining the data from different addresses may take different lengths of time which may depend on the particular address to be read or may depend on the current status of the read device itself Data at one address may be available immediately, data at another address may be available in one clock period, data at another address may be available in two clock periods, and so on. In fact, the time in which it takes to obtain certain data may not be even ascertainable until the data has been obtained.
Consequently, it is necessary in prior art interface arrangements to utilize the standard method for synchronizing handshake signals. That is, a read signal is provided by the requesting system, synchronized through two stages of flip-flops, and the system furnishing the data begins to obtain the data in response to the signal. When the data is obtained, it is placed on the data bus for transmitting to the requesting system; and, an acknowledge signal is sent to the requesting system and synchronized through two additional stages of flip-flops.